Hardware-software Partitioning Algorithm Based on Binary Search Trees and Genetic Algorithm to Optimize Logic Area for Sopc
نویسندگان
چکیده
This paper presents an approach based on hardware/software partitioning to minimize the logic area of System on a Programmable Chip (SOPC) while respecting a time constraint. Our contribution focuses on introducing a new hardware/software partitioning algorithm. This algorithm is based on the principle of Binary Search Trees (BST) and genetic algorithms. It aims to define the tasks that will run on the Hardware (HW) part and those that will run on the Software (SW) part. The proposed algorithm will determine the best partition that will reduce the number of tasks used by the HW and increase the number of tasks used by the SW and thereafter the area will be reduced. The results show that our algorithm significantly reduces the logic area compared to other well known algorithms.
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